Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance

An extremely thin semiconductor-on-insulator (ETSOI) device comprising:

• a. a back gate layer on a substrate superimposed by a thin insulator buried oxide (BOX) layer having a thickness less than 30 nm;
• b. an ETSOI layer on top of said thin insulator BOX layer;
• c. a field effect transistor (FET) device on said ETSOI layer having a thickness ranging between 2 nm and 10 nm, provided with source and drain regions, and a gate stack insulated from a drain and a source by spacers;
• and
• d. a dielectric portion in said substrate and in a region directly beneath said source and said drain are self-aligned to said gate stack, wherein said source and drain regions are separated from said back gate layer by a combination of said thin insulator BOX layer and said dielectric portion,
• wherein said back gate layer has a thickness ranging between 20 nm and 200 nm and having an active dopant concentration exceeding 1×1018 cm−3.