High voltage devices, systems, and methods for forming the high voltage devices

A high voltage (HV) device comprising:

• a gate dielectric structure over a substrate, the gate dielectric structure having a first portion and a second portion, the first portion having a first thickness and being over a first well region of a first dopant type in the substrate, the second portion having a second thickness and being over a second well region of a second dopant type, the first thickness being larger than the second thickness;
• a gate electrode disposed over the gate dielectric structure;
• at least one source/drain (S/D) region disposed within the second well region;
• another S/D region within the first well region;
• and
• a metallic layer electrically coupled with the at least one S/D region, the metallic layer overlapping the gate electrode and extending along a direction of a channel under the gate dielectric structure,
• wherein the metallic layer has a first edge, the gate electrode has a second edge, and the another S/D region has a third edge, the first edge is directly over a gap region defined by the second edge and the third edge, the gate electrode and the another S/D region are positioned outside the gap region, and the first edge is closer to the third edge than to the second edge.

A method for forming a high voltage (HV) device, the method comprising:

• forming a gate dielectric structure over a substrate, the gate dielectric structure having a first portion and a second portion, the first portion having a first thickness and being over a first well region of a first dopant type in the substrate, the second portion having a second thickness and being over a second well region of a second dopant type, the first thickness being larger than the second thickness;
• forming a gate electrode over the gate dielectric structure;
• forming a source/drain (S/D) region within the first well region;
• forming a dielectric layer directly on at least a portion of an upper surface of the gate electrode;
• and
• forming a metallic layer directly on the dielectric layer and electrically coupled with the gate electrode, the metallic layer overlapping the gate electrode and extending along a direction of a channel under the gate dielectric structure,
• wherein an edge of the metallic layer is directly over a gap region defined by an edge of the gate electrode and an edge of the S/D region, and the gate electrode and the S/D region are positioned outside the gap region.