High voltage device
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsGuowei Zhang, Purakh Raj Verma
Life of this patent
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Abstract
A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.
Claims20
A device comprising:
- a substrate prepared with an active device region, wherein the active device region includes a gate, the gate including a gate electrode over a gate dielectric;
- a doped channel well disposed in the substrate adjacent to a first edge of the gate, the first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate, the first edge of the gate and channel edge beneath the gate define a channel of the device, wherein the channel is displaced from a first heavily doped region adjacent to the first edge of the gate;
- and
- a doped drift well adjacent to a second edge of the gate.
A device comprising:
- a substrate prepared with an active device region, wherein the active device region includes a gate, the gate including a gate electrode over a gate dielectric;
- a doped channel well disposed in the substrate adjacent to a first edge of the gate, wherein the first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate, the first edge of the gate and channel edge beneath the gate define a channel of the device, wherein the channel is displaced from a first heavily doped region adjacent to the first edge of the gate;
- a doped drift well adjacent to a second edge of the gate;
- and
- a drift isolation region in the doped drift well.
A semiconductor device comprising:
- a substrate prepared with an active device region, wherein the active device region includes a gate, the gate including a gate electrode over a gate dielectric;
- first and second heavily doped regions adjacent to first and second edges of the gate;
- a doped channel well disposed in the substrate adjacent to the first edge of the gate, wherein the first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate, the first edge of the gate and channel edge beneath the gate define a channel of the device, wherein the channel is displaced from the first heavily doped region adjacent to the first edge of the gate;
- and
- a doped drift well adjacent to a second edge of the gate, wherein a drift isolation region is disposed in the doped drift well.
Dependencies are inferred from the claim text.