Method of manufacturing NMOS transistor with low trigger voltage
AssigneeUnited Microelectronics Corp.
InventorsLu-An Chen, Tai-Hsiang Lai, Tien-Hao Tang
Life of this patent
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Abstract
A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.
Claims10
An NMOS (n-type metal-oxide-semiconductor) comprising:
- a P-substrate;
- an N-well on the P-substrate;
- an N-drift region on the N-well;
- an n+ drain on the N-drift region;
- a plurality of first contacts on the n+ drain arranged along a longitudinal direction;
- a P-body on the N-well;
- a source on the P-body, the source comprising a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction;
- a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region, wherein the plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region are separate from one another;
- a polygate on the P-body;
- and
- a gate oxide between the polygate and the source.
Dependencies are inferred from the claim text.