US 8,507,980 B2 · Semiconductor devices having bit line interconnections with increased width and reduced distance from corresponding bit line contacts and methods of fabricating such devices

Abstract

A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.

Claims18

Dependent claims

A semiconductor device comprising:

a substrate including a cell area comprising a cell active region and a cell isolation region;
a cell gate electrode buried in the substrate and crossing the cell active region;
a drain region in the cell active region adjacent the cell gate electrode;
an insulation layer on the substrate, the insulation layer having a contact hole exposing the drain region;
a bit line contact in the contact hole;
and
a bit line,
wherein the bit line comprises a first bit line portion on the bit line contact and a second bit line portion on the insulation layer, and a top surface of the first bit line portion is lower than a top portion of the second bit line portion.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor devices having bit line interconnections with increased width and reduced distance from corresponding bit line contacts and methods of fabricating such devices

Life of this patent

Semiconductor devices having bit line interconnections with increased width and reduced distance from corresponding bit line contacts and methods of fabricating such devices

Life of this patent

Abstract

Claims18