Fin-like field effect transistor (FinFET) non-volatile random access memory (NVRAM) device with bottom erase gate

A non-volatile random access memory (NVRAM) device comprising:

• a semiconductor substrate;
• an insulator layer disposed over the semiconductor substrate;
• a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region;
• a first control gate disposed along one sidewall of the channel region of the fin structure;
• a second control gate disposed opposite the first control gate, the second control gate being disposed along another sidewall of the channel region of the fin structure;
• a first charge storing node and a second charge storing node, wherein the first charge storing node is disposed between the sidewall of the channel region of the fin structure and the first control gate, and wherein the second charge storing node is disposed between the another sidewall of the channel region of the fin structure and the second control gate;
• and
• an erase gate disposed in the semiconductor substrate below the channel region of the fin structure, wherein the erase gate is a doped region disposed in the semiconductor substrate.

A method comprising:

• forming a doped region in a substrate through an insulator layer of the substrate such that the doped region is formed below the insulator layer;
• forming a fin structure over the insulator layer and the doped region, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the channel region of the fin structure is disposed over the doped region;
• and
• forming a gate structure adjacent to the channel region of the fin structure, wherein the gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer.