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US 8,507,968 B2Granted
Memristive transistor memory
AssigneeHewlett-Packard Development Company, L.P.
InventorsDmitri B. Strukov, Philip J. Kuekes, Duncan Stewart, Zhiyong Li
Life of this patent
Estimating the term…
Abstract
A memory device (100) includes a semiconductor wire including a source region (132), a drain region (134), and a channel region (130) between the source region (132) and the drain region (134). A gate structure that overlies the channel region includes a memristive portion (120) and a conductive portion (110) overlying the memristive portion (120).
Claims18
A memory device comprising:
- a semiconductor including a source region, a drain region, and a channel region between the source region and the drain region;
- a first gate structure overlying the channel region, wherein the first gate structure comprises:
- a first memristive portion overlying the channel region;
- and
- a first conductive portion overlying the first memristive portion;
- and
- a second gate structure underlying the channel region, wherein the second gate structure comprises:
- a second memristive portion underlying the channel region;
- and
- a second conductive portion underlying the second memristive portion.
7 more elements
A memory device comprising:
- a first set of gate wires, wherein each of the gate wires comprises a first memristive portion, a conductive portion, and a second memristive portion that is on an opposite side of the conductive portion of the gate wire from the first memristive portion;
- a first set of semiconductor wires that cross the gate wires and are adjacent to the first memristive portions, wherein a channel region resides in the semiconductor wires at each location where the first set of the semiconductor wires cross the gate wires, and source/drain regions are on either side of the channel regions;
- and
- a second set of semiconductor wires that are adjacent to the second memristive portions of the gate wires.
1 more element
A process for fabricating a memory device comprising:
- forming a first plurality of semiconductor wires;
- forming over the semiconductor wires a first layer of a first material capable of transporting and hosting dopants;
- creating a second layer containing dopants that are able to flow into the first layer in response to an applied electric field;
- forming a conductive layer on the second layer;
- creating a third layer containing the dopants, the third layer being on the conductive layer;
- and
- forming a fourth layer of the first material on the third layer;
- patterning the first layer, the second layer, the conductive layer, the third layer, and the fourth layer to form a first plurality of gate wires that cross the first plurality of semiconductor wires;
- and
- doping source/drain regions in the first plurality of semiconductor wires using the gate wires to mask the implanting;
- and
- forming a second plurality of semiconductor wires crossing over the first plurality of gate wires.
9 more elements
Dependencies are inferred from the claim text.