Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same

An access device, comprising:

• a conductive line disposed over a substrate;
• a transistor comprising a channel region interposed between a source region and a drain region, the source region disposed on the conductive line;
• and
• an access line disposed on sidewalls of the transistor, the access line being operably coupled to a voltage source.

A semiconductor array comprising:

• at least one conductive line disposed on an electrically insulative material overlying a logic device formed on a wafer;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a first doped region interposed between second doped regions, the first doped region and the second doped regions being oppositely doped;
• and
• at least one access line disposed on sidewalls of the plurality of transistors.

A semiconductor array comprising:

• at least one conductive line;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a first doped region interposed between second doped regions, the first doped region and the second doped regions being oppositely doped, the plurality of transistors comprising an array of transistors aligned in a plurality of rows extending in a first direction and aligned in a plurality of columns extending in a second direction perpendicular to the first direction;
• and
• at least one access line disposed on sidewalls of the plurality of transistors.

A semiconductor array comprising:

• at least one conductive line;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a first doped region interposed between second doped regions, the first doped region and the second doped regions being oppositely doped, sidewalls of each of the plurality of transistors being substantially aligned with sidewalls of the at least one conductive line;
• and
• at least one access line disposed on sidewalls of the plurality of transistors.

A semiconductor array comprising:

• at least one conductive line;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a first doped region interposed between second doped regions, the first doped region and the second doped regions being oppositely doped, each of the plurality of transistors comprises comprising a pillar of semiconductive material overlying the at least one conductive line, sidewalls of the pillar of semiconductive material being substantially aligned with sidewalls of the at least one conductive line;
• and
• at least one access line disposed on sidewalls of the plurality of transistors.

A semiconductor array comprising:

• at least one conductive line;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a first doped region interposed between second doped regions, the first doped region and the second doped regions being oppositely doped;
• at least one access line disposed on sidewalls of the plurality of transistors;
• and
• at least one logic device disposed under the at least one conductive line.

A semiconductor device, comprising:

• an array of access devices comprising:
• a plurality of transistors substantially aligned in a plurality of rows in a first direction and in a plurality of columns in a second direction perpendicular to the first direction, each of the plurality of transistors comprising a channel region interposed between a source region and a drain region;
• and
• at least one access line electrically coupled with at least one of the plurality of transistors;
• and
• a plurality of conductive lines, each conductive line of the plurality of conductive lines electrically coupled with the source region of the plurality of transistors in one of the plurality of rows.

A system comprising:

• at least one memory semiconductor array;
• and
• at least one semiconductor array operably coupled to the at least one memory semiconductor array and comprising:
• at least one conductive line;
• a plurality of transistors disposed on the at least one conductive line, each of the plurality of transistors comprising a channel region interposed between a source region and a drain region;
• and
• at least one access line associated with the plurality of transistors.