Nonvolatile semiconductor memory device comprising memory cell array having multilayer structure

A nonvolatile semiconductor memory device, comprising a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other,

• the memory cells having a variable resistance element and a non-ohmic element laminated in a direction in which the memory cell layers are laminated,
• the variable resistance element and the non-ohmic element of the memory cells in a certain memory cell layer being laminated in the same order and have substantially the same size as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer,
• the first or second wires being shared by a first memory cell layer and a second memory cell layer of the plurality of memory cell layers, the first and second memory cell layers being adjacent in the direction in which the layers are laminated, and
• the memory cells being tapered in such a manner that an area in a cross section gradually becomes smaller from a bottom of the first memory cell layer towards the top of the second memory cell layer.