Alignment tolerant semiconductor contact and method
AssigneeGlobalfoundries Inc.
InventorsAndré P. Labonté, Richard S. Wise
Life of this patent
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AssigneeGlobalfoundries Inc.
InventorsAndré P. Labonté, Richard S. Wise
Estimating the term…
An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
A method for forming an alignment tolerant electrical contact to a contact region of an underlying substrate, comprising:
A method for forming an integrated circuit having a field effect transistor (FET), comprising:
Dependencies are inferred from the claim text.