Semiconductor device including transistors of different junction depth, and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorHiroki Shirai
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Abstract
A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing at least a first impurity, and a second transistor formed in a logic region, and having a second source/drain region containing at least a second impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by an impurity and is deeper than the junction depth of the second source/drain region.
Claims10
A semiconductor device comprising a DRAM region and a logic region embedded together therein, said semiconductor comprising:
- a substrate comprising said DRAM region and said logic region formed therein;
- a first transistor formed in said DRAM region of said substrate, and comprising a first source/drain region, said first source/drain region comprising:
- a first impurity ion;
- and
- a second impurity ion different from said first impurity ion;
- and
- a second transistor formed in said logic region of said substrate, and comprising a second source/drain region, said second source/drain region comprising:
- said first impurity ion;
- and
- said second impurity ion,
- wherein each of said first source/drain region and said second source/drain region of said substrate comprises a suicide layer respectively formed in a surficial portion thereof,
- said first source/drain region has a deepest junction depth which is determined by said first impurity ion contained by said first source/drain region,
- said second source/drain region has a deepest junction depth which is determined by said first impurity ion contained by said second source/drain region, and
- said deepest junction depth of said first source/drain region is deeper than said deepest junction depth of said second source/drain region.
A method of manufacturing a semiconductor device comprising a DRAM region and a logic region embedded together therein, the method comprising:
- forming a gate electrode in each of said DRAM region and said logic region formed in a substrate;
- introducing a first impurity ion and a second impurity ion different from said first impurity ion, by ion implantation, into said logic region and into said DRAM region, while using said gate electrode as a mask;
- allowing said first impurity ion and said second impurity ion to diffuse by annealing, to thereby form a first source/drain region and a second source/drain region respectively in said DRAM region and said logic region;
- and
- forming a silicide layer in a surficial portion of each of said first source/drain region and said second source/drain region,
- wherein in said introducing said first impurity ion and said second impurity ion, by ion implantation, said first impurity ion is introduced to said DRAM region at a first energy and said first impurity ion is introduced to said logic region at a second energy different from said first energy, so that from said introducing, a deepest junction depth in said first source/drain region is deeper than a deepest junction depth in said second source/drain region.
Dependencies are inferred from the claim text.