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US 8,507,343 B2Granted
Variable resistance memory device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorJung-in Kim
Life of this patent
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Abstract
In a variable resistance memory device and a method of manufacturing the variable resistance memory device, the generation of a seam, or void, is avoided in the device that, if present, may otherwise reduce the reliability of the resulting device.
Claims15
A method of manufacturing a variable resistance memory device comprising:
- forming an inter-insulating layer including a hole on a substrate;
- forming a selection device in a lower portion of the hole;
- forming a first electrode including a first part electrically connected to the selection device and contacting a side surface of upper portion of the hole and a second part extending from the first part to be parallel to a surface of the substrate;
- forming a first insulating pattern including a third part contacting the first part and a fourth part extending from the third part to contact the second part and having the same thickness as the third part, the first insulating pattern being disposed on the first electrode;
- forming a trench limited by the first insulating pattern and the inter-insulating layer by partly etching a sidewall of the inter-insulating layer facing the third part;
- forming a second insulating pattern filling the trench;
- and
- forming a variable resistance pattern and an upper electrode on the first electrode.
5 more elements
A method of forming a variable-resistance integrated circuit memory in a wafer, comprising:
- forming a hole within an inter-insulating layer formed on a substrate;
- forming a selection device in a lower portion of the hole;
- forming an electrode layer in the hole over the selection device;
- forming an insulating layer over the electrode layer in the hole;
- burying the hole with a relatively low-viscosity material;
- forming a trench in the low-viscosity material and in a portion of the electrode layer and in a portion of the insulating layer and in a portion of the inter-insulating layer, leaving at least a vertical segment of electrode layer and a vertical segment of insulating layer in the hole;
- removing the low-viscosity material and filling the remnant of the trench with a second insulating layer;
- planarizing the wafer to expose a first electrode pattern, a first insulating pattern, and a second insulating pattern, the tops of which are all substantially at the same height as the top of the inter-insulating layer;
- forming a variable resistance pattern on top of and in contact with the top of the first electrode pattern;
- and
- forming a second electrode pattern on top of the variable resistance pattern.
8 more elements
Dependencies are inferred from the claim text.