Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device

A method of forming a device, said method comprising:

• forming multiple gates on a semiconductor layer to define channel regions in said semiconductor layer for multiple planar field effect transistors;
• after said forming of said gates, forming source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor;
• and
• forming, over said multiple planar field effect transistors, a conformal conductive layer that is electrically isolated from said gates and in contact with said source/drain regions, said conformal conductive layer being formed to have a higher resistance than said channel regions when said multiple planar field effect transistors are in an “on” state and a lower resistance than said channel regions when said multiple planar field effect transistors are in an “off” state.

A method of forming a device, said method comprising:

• forming a semiconductor fin on an isolation layer;
• forming multiple gates on said semiconductor fin, said gates defining channel regions in said semiconductor fin for multiple non-planar field effect transistors connected in a series;
• after said forming of said multiple gates, forming source/drain regions within said semiconductor fin on opposing sides of each of said channel regions such that each portion of said semiconductor fin between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor;
• and
• forming, over said multiple non-planar field effect transistors, a conformal conductive layer that is electrically isolated from said gates and in contact with said source/drain regions
• said conformal conductive layer being formed to have a higher resistance than said channel regions when said multiple non-planar field effect transistors are in an “on” state and a lower resistance than said channel regions when said multiple non-planar field effect transistors are in an “off” state.