Chip package and method for forming the same
OwnerChao-Yen Lin, Yi-Hang Lininventors
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Abstract
An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
Claims17
A method for forming a chip package comprising:
- providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
- providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
- forming a recess from the upper surface of the semiconductor substrate;
- thinning the semiconductor substrate before the recess is formed;
- forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
- forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate;
- and
- dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
A method for forming a chip package, comprising:
- providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
- providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
- forming a recess from the upper surface of the semiconductor substrate;
- forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
- forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate, and wherein the conducting layer extends on the bottom of the recess;
- and
- dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
A method for forming a chip package comprising:
- providing a semiconductor substrate having an upper surface and a lower surface, wherein the semiconductor substrate comprises at least a device region or sensing region and at least a conducting pad on the upper surface of the semiconductor substrate;
- providing a carrier substrate and disposing the semiconductor substrate overlying the carrier substrate;
- forming a recess from the upper surface of the semiconductor substrate, wherein the recess extends into the carrier substrate;
- forming an insulating layer overlying the upper surface of the semiconductor substrate and within the recess;
- forming a conducting layer overlying the insulating layer, wherein the conducting layer is electrically connected to the conducting pad and extends from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate;
- and
- dicing the carrier substrate from a bottom of the recess to form a plurality of separate chip packages.
Dependencies are inferred from the claim text.