Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• forming a hard mask layer over a semiconductor substrate having an underlying layer;
• first photo-etching on a first photoresist film coated on the hard mask layer with a first exposure mask having a first space pattern formed in a first direction to form a first photoresist pattern;
• etching the hard mask layer with the first photoresist pattern as a first etching mask to form a hard mask pattern;
• second photo-etching on a second photoresist film coated over the resulting structure having the hard mask pattern with a second exposure mask different from the first exposure mask , the second exposure mask having a second space pattern formed in a second direction intersected with the first direction;
• and
• etching the underlying layer with the second photoresist pattern and the hard mask pattern, as a second etching mask to form a contact hole,
• wherein the first direction is a minor axis direction of a circuit pattern where the contact hole is formed and the second direction is a major axis direction of the circuit pattern, and
• wherein a contrast slope of the first exposure mask is larger than a contrast slope of the second exposure mask, such that a degree of diffraction of the first exposure mask is less than a degree of diffraction of the second exposure mask.

A method of manufacturing a semiconductor device, the method comprising:

• forming a plurality of hard mask layers on a semiconductor substrate having an underlying layer;
• repeatedly photo-etching the hard mask layers with a plurality of exposure masks to form a plurality of hard mask patterns;
• and
• etching the underlying layer with the hard mask patterns as an etching mask to form a contact hole,
• wherein at least one of the plurality of exposure masks has a first space pattern formed in a minor axis direction of a circuit pattern where the contact hole is formed and at least one of the other exposure masks has a second space pattern formed in a major axis direction of the circuit pattern, and
• wherein a contrast slope of the mask having a first space pattern is larger than a contrast slope of the mask having a second space pattern, such that a degree of diffraction of the first exposure mask is less than a degree of diffraction of the second exposure mask.