Apparatus and method for providing digital representation of time difference between clocks

A method for determining a digital representation of a time difference between a reference signal having a reference signal period and an input signal having an input signal period, the method comprising:

• receiving the reference signal and the input signal;
• receiving state vectors corresponding to a plurality of states periodically traversed by a continuously free-running finite state machine (FSM) in a predetermined order, each state vector being held for a state dwell time occurring between state transitions;
• determining a plurality of state transition counts corresponding to a plurality of counting intervals, the state transition counts being numbers of state transitions occurring in the FSM during the corresponding counting intervals, wherein each counting interval corresponds to the time difference between the reference signal and the input signal for each corresponding reference signal period;
• producing weighted sums of the numbers of the state transitions, each weighted sum being indicative of a ratio between the corresponding counting interval and the state dwell time;
• and
• outputting an output signal estimating the time difference between the reference signal and the input signal based on the ratio between the corresponding counting interval and the state dwell time,
• wherein a period of the FSM is independent of the reference signal period.

An all digital phase lock loop (ADPLL), comprising:

• a time-to-digital converter (TDC) configured to provide a digital time difference signal representing a time difference between a reference signal and an input signal based on an analog output signal of the ADPLL, the reference signal having a reference signal period and the input signal having an input signal period;
• and
• a controllable oscillator configured to provide the analog output signal, the analog output signal having a frequency controlled by the digital time difference signal, wherein the TDC comprises:
• a free-running finite state machine (FSM) configured to traverse a plurality of states in a predetermined order, the plurality of states having corresponding state vectors, each state vector being held for a state dwell time;
• a timing circuit configured to receive the reference signal, the input signal and the state vectors, and to determine state transition counts equal to a number of state transitions that occur during a counting interval at each reference signal period, wherein the counting interval corresponds to the time difference between the reference signal and the input signal;
• and
• a digital low-pass filter configured to receive the state transition counts corresponding to the reference signal periods, and to provide an output value comprising weighted sums of the state transition counts, the output value being proportional to the time difference between the reference signal and the input signal, wherein a period of the FSM is independent of the reference signal period.