Non-volatile semiconductor memory storing an inverse map for rebuilding a translation table

A non-volatile semiconductor memory comprising:

• a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address;
• a volatile memory;
• and
• control circuitry operable to:
• upon a power-up of the non-volatile semiconductor memory, generate, in the volatile memory, a translation table for mapping logical addresses to physical addresses in the non-volatile memory array, the control circuitry operable to generate by at least:
• reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments;
• and
• in response to determining that the memory segment corresponding to the logical address is valid, updating the translation table using the logical address.