Simultaneous wafer bonding and interconnect joining
AssigneeTessera, Inc.
InventorsVage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
Life of this patent
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Abstract
Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
Claims48
A method of forming a microelectronic assembly comprising the steps of:
- providing a microelectronic element having a major surface, and a dielectric layer and at least one bond pad exposed at the major surface, the microelectronic element containing a plurality of active circuit elements, wherein the dielectric layer is separated in a direction parallel to the major surface from the at least one bond pad by a gap;
- providing a second element having a coefficient of thermal expansion of less than 10 ppm/° C., the second element having a major surface and a dielectric layer exposed at the major surface of the second element;
- forming a first metal layer such that a first portion of the first metal layer overlies the at least one bond pad and a second portion of the first metal layer overlies the dielectric layer of the microelectronic element, the first and second portions being separated by the gap;
- forming a second metal layer overlying the dielectric layer of the second element;
- and
- joining the first metal layer with the second metal layer.
A microelectronic assembly comprising:
- a microelectronic element having a major surface, and a dielectric layer and at least one bond pad exposed at the major surface, the microelectronic element containing a plurality of active circuit elements;
- a second element having a coefficient of thermal expansion of less than 10 ppm/° C., the second element having a major surface, and at least one bond pad and a dielectric layer exposed at the major surface thereof;
- a first metal layer overlying the at least one bond pad and the dielectric layer of the microelectronic element, wherein a gap is formed in the first metal layer between the at least one bond pad and the dielectric layer;
- a second metal layer overlying the at least one bond pad and the dielectric layer of the second element;
- and
- wherein first portions of the first and second metal layers overlying the dielectric layers are joined together and second portions of the first and second metal layers overlying the at least one bond pads and being separate from the first portions are joined together so as to mechanically and electrically connect the microelectronic element with the second element.
A microelectronic assembly comprising:
- a microelectronic element having a major surface and a dielectric layer exposed at the major surface;
- and
- a second element having a major surface and a dielectric layer exposed at the major surface of the second element;
- the major surfaces of the microelectronic and second elements confronting one another with a plurality of metal elements disposed between the dielectric layers, the metal elements being electrically isolated from the microelectronic element,
- wherein the metal elements join the microelectronic and second elements with one another,
- wherein on each of the microelectronic element and the second element, a gap is formed along the major surface between one or more of the metal elements and an adjacent portion of the dielectric layer,
- wherein the gap is large enough to provide a relief volume into which a reflowable metal can flow from between the dielectric layers of the microelectronic and second elements, the relief volume being sufficient to compensate for a sum of the total variation in co-planarity of top surfaces of the metal elements and the dielectric layer overlying the major surface of the microelectronic element, and the total variation in co-planarity of top surfaces of the metal elements and the dielectric layer overlying the major surface of the second element.
Dependencies are inferred from the claim text.