Implementing electronic chip identification (ECID) exchange for network security

A circuit for implementing electronic chip identification (ECID) exchange for network security in a multiple-path local rack interconnect system including a plurality of interconnect chips, and a plurality of serial links connected between each of said plurality of interconnect chips;

• said circuit comprising:
• each interconnect chip including an ECID for the interconnect chip, each said ECID being unique and unchangeable binary data and being permanently stored on each said interconnect chip;
• and each said ECID unique and unchangeable binary data being directly available as parallel outputs for each said interconnect chip;
• a system management processor connected to each said interconnect chip and including a system list for the multiple-path local rack interconnect system;
• each said interconnect chip including a network manager using End-to-End (ETE) small control packets for network management and control functions in the multiple-path local rack interconnect system;
• said network manager of each said interconnect chip,
• sending predefined exchange identification (EXID) messages including said ECID unchangeable binary data across said links to other interconnect chips in the interconnect system;
• comparing a received EXID with said system list for the interconnect system to verify validity of the sending interconnect chip and for selectively enabling each said interconnect chip
• periodically transmitting said EXID messages across selected links to other interconnect chips in the interconnect system;
• said selected links including links to disabled ports having a good link heartbeat;
• and
• responsive to the received EXID being identified as valid, writing a port enable configuration bit for the sending interconnect chip.

A multiple-path local rack interconnect system comprising:

• a plurality of interconnect chips;
• a plurality of serial links connected between each of said plurality of interconnect chips;
• each of said interconnect chips including an electronic chip identification (ECID) for the interconnect chip, each said ECID being unique and unchangeable binary data and being permanently stored on each said interconnect chip;
• and each said ECID unique and unchangeable binary data being directly available as parallel outputs for each said interconnect chip;
• a system management processor connected to each said interconnect chip and including a system list for the multiple-path local rack interconnect system;
• each said interconnect chip including a network manager using End-to-End (ETE) small control packets for network management and control functions in the multiple-path local rack interconnect system;
• said network manager of each said interconnect chip,
• sending predefined exchange identification (EXID) messages including said ECID unchangeable binary data across said links to other interconnect chips in the interconnect system;
• comparing a received EXID with said system list for the interconnect system to verify validity of the sending interconnect chip and for selectively enabling each said interconnect chip
• periodically transmitting said EXID messages across selected links to other interconnect chips in the interconnect system;
• said selected links including links to disabled ports having a good link heartbeat;
• and
• responsive to the received EXID being identified as valid, writing a port enable configuration bit for the sending interconnect chip.

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing electronic chip identification (ECID) exchange for network security in a multiple-path local rack interconnect system, said circuit comprising:
• each interconnect chip including an ECID for the interconnect chip, each said ECID being unique and unchangeable binary data and being permanently stored on each said interconnect chip;
• and each said ECID unique and unchangeable binary data being directly available as parallel outputs for each said interconnect chip;
• a system management processor connected to each said interconnect chip and including a system list for the multiple-path local rack interconnect system;
• each said interconnect chip including a network manager using End-to-End (ETE) small control packets for network management and control functions in the multiple-path local rack interconnect system;
• said network manager of each said interconnect chip,
• sending predefined exchange identification (EXID) messages including said ECID unchangeable binary data across said links to other interconnect chips in the interconnect system;
• and
• comparing a received EXID with said system list for the interconnect system to verify validity of the sending interconnect chip and for selectively enabling each said interconnect chip,
• periodically transmitting said EXID messages across selected links to other interconnect chips in the interconnect system;
• said selected links including links to disabled ports having a good link heartbeat;
• and
• responsive to the received EXID being identified as valid, writing a port enable configuration bit for the sending interconnect chip, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.