Efficient and self-balancing verification of multi-threaded microprocessors

A computer program product comprising a non-transitory computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

• generate non-irritator thread code for execution by a non-irritator thread of the multi-threaded multiprocessor data processing system;
• generate irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system, wherein the non-irritator thread code is different from the irritator thread code;
• wherein
• the irritator thread loop has multiple iterations and the non-irritator thread is a random or a controlled instruction stream;
• instantiate the non-irritator thread to execute the non-irritator thread code;
• instantiate the one or more irritator threads to execute the irritator thread code;
• determine whether the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code;
• and
• responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, perform an operation to terminate the execution of the irritator thread code by the one or more irritator threads, wherein
• the irritator thread code is restricted such that the irritator thread code does not cause any unexpected exceptions, does not modify any of memory that is read by the non-irritator thread, does not modify any core level register, or that any architected results of executing the irritator thread code goes undefined.

An apparatus, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
• generate non-irritator thread code for execution by a non-irritator thread of the multi-threaded multiprocessor data processing system;
• generate irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system;
• wherein the non-irritator thread code is different from the irritator thread code;
• wherein
• the irritator thread loop has multiple iterations and the non-irritator thread is a random or a controlled instruction stream;
• instantiate the non-irritator thread to execute the non-irritator thread code;
• instantiate the one or more irritator threads to execute the irritator thread code;
• determine whether the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code;
• and
• responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, perform an operation to terminate the execution of the irritator thread code by the one or more irritator threads, wherein
• the irritator thread code is restricted such that the irritator thread code does not cause any unexpected exceptions, does not modify any of memory that is read by the non-irritator thread, does not modify any core level register, or that any architected results of executing the irritator thread code goes undefined.