Automation using spine routing

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• and
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,
• the first direction is orthogonal to the second direction, and
• the route area in the second direction extends between the most oppositely disposed in the second direction of the at least two pins.

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and
• the first direction is orthogonal to the second direction;
• and
• determining a position in the second direction for the spine interconnect to reduce an average length of the plurality of stitching interconnects.

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• and
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and
• the first direction is orthogonal to the second direction, and
• the position of the spine interconnect in the second direction being a quotient of the sum of the positions of the N pins in the second direction and N.

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• and
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction, and
• the first direction is orthogonal to the second direction, and
• the position of the spine interconnect in the second direction is a closest position outside the at least one forbidden area to a weighted average position in the second direction of the at least two pins positions.

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• and
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,
• the first direction is orthogonal to the second direction;
• and
• determining if a path of each of the plurality of stitching interconnects is unobstructed by the at least one obstacle.

A method for routing at least one interconnect of an integrated circuit comprising:

• identifying N pins to couple;
• calculating a rectangular route area to comprise the positions in a first direction of the N pins;
• determining if at least one forbidden area is located within the route area;
• using at least one computer processor, routing outside of the at least one forbidden area a spine interconnect extending in the first direction an entire length of the route area in the first direction;
• and
• routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
• wherein the at least one forbidden area being a rectangular area to include at least one obstacle and extend in the first direction an entire length of the route area in the first direction,
• the first direction is orthogonal to the second direction, and
• an edge of the route area being an edge of a chip, the edge of the chip includes one of the at least one pins.

A method comprising:

• providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;
• using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;
• within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;
• generating a first plurality of stitch polygons to couple each of the first pins to the first polygon;
• and
• generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,
• wherein a length-to-width ratio of the routing area is at least four-to-one.

A method comprising:

• providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;
• using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;
• within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;
• generating a first plurality of stitch polygons to couple each of the first pins to the first polygon;
• and
• generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,
• wherein at least one of the stitch polygons has a length greater than its width, and its length is perpendicular to the length of the spine polygons.

A method comprising:

• providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;
• using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;
• within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;
• generating a first plurality of stitch polygons to couple each of the first pins to the first polygon;
• and
• generating a second plurality of stitch polygons to couple each of the second pins to the second polygon,
• wherein the routing area comprises an obstacle polygon and generating a first plurality of stitch polygons to couple each of the first pins to the first polygon comprises:
• performing one or more flood operations to route at least one of the stitch polygons around the obstacle.

A method comprising:

• providing a routing area having a length dimension greater than a width dimension, wherein the routing area comprises a plurality of first pins to be coupled together using a first interconnect, and a plurality of second pins to be coupled together using a second interconnect;
• using at least one computer processor, within the routing area, generating a first spine polygon of the first interconnect having a plurality of straight edges extending the length of the routing area and a uniform first width between the straight edges;
• within the routing area, generating a second spine polygon of the second interconnect, parallel to the first spine polygon, having a plurality of straight edges extending the length of the routing area and the uniform first width between the straight edges;
• generating a first plurality of stitch polygons to couple each of the first pins to the first polygon;
• generating a second plurality of stitch polygons to couple each of the second pins to the second polygon;
• and
• providing a forbidden area within the routing area, wherein the first and second spine polygons are positioned within the routing area and outside the forbidden area.