Automatically creating vias in a circuit design

A computer-implemented method for automatically generating electrical connections between circuit components in a circuit design, the method comprising:

• utilizing a computer to perform:
• determining an overlap area between at least two circuit components in a layout representation of the circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in a schematic representation of the circuit design, and wherein the at least two circuit components are part of a first net in the schematic representation of the circuit design;
• and
• automatically inserting a conducting via in the overlap area between the at least two circuit components in the layout representation of the circuit design, based on the information regarding allocation of nets in the schematic representation of the circuit design, wherein the conducting via connects at least two layers in the layout representation of the circuit design without the at least two layers having previously been identified as needing to be connected to each other in the overlap area.

A computer-implemented method for automatically generating electrical connections between circuit components in a circuit design, the method comprising:

• utilizing a computer to perform:
• determining an overlap area between at least two circuit components in the circuit design, wherein the circuit design comprises information regarding allocation of nets to circuit components in the circuit design, and wherein the at least two circuit components are part of a first net and have no other circuit components connected to a different net located in the overlap area between the at least two circuit components;
• and
• automatically inserting a conducting via structure in the circuit design based on user defined design rules and the information regarding allocation of nets to circuit components in the circuit design, wherein the conducting via structure comprises a plurality of vias and a via cap in the overlap area between the at least two circuit components, wherein the plurality of vias connect at least two layers in the circuit design.

A non-transitory computer-readable memory medium that stores program instructions executable by a processor to perform:

• determining that a plurality of metallic conducting traces comprised in two or more layers of a circuit design overlap, wherein the circuit design comprises information indicating that the plurality of metallic conducting traces are part of a first net;
• determining whether there are no traces of other nets in the overlap of the plurality of metallic conducting traces;
• determining whether a conducting via can automatically be created in the overlap between the plurality of metallic conducting traces in response to determining that there are no traces of other nets in the overlap of the plurality of metallic conducting traces;
• and
• inserting at least one conducting via in the overlap between the plurality of metallic conducting traces in response to determining that the conducting via can be automatically created in the overlap, wherein said inserting is based on the information indicating that the plurality of metallic conducting traces are part of the first net.