Automated framework for programmable logic device implementation of integrated circuit design

A non-transitory computer accessible storage medium storing:

• one or more design files describing at least a portion of an integrated circuit using a hardware description language (HDL);
• one or more user-generated control files specifying modifications to the at least a portion of the integrated circuit, wherein at least one of the user-generated control files specifies modifications to HDL code in the one or more design files;
• and
• a plurality of instructions which, when executed, process the one or more design files and the one or more user-generated control files to generate an implementation of the portion of the integrated circuit in one or more programmable logic devices, wherein said generating the implementation includes automatically performing the specified modifications to the HDL code in the one or more design files.

A non-transitory computer accessible storage medium storing:

• one or more design files describing at least a portion of an integrated circuit using a hardware description language (HDL);
• one or more user-generated control files specifying modifications to HDL code in the one or more design files for field programmable gate array (FPGA) implementation;
• and
• a plurality of instructions which, when executed:
• automatically modify the HDL code in the one or more design files based on the modifications specified by the one or more control files;
• generate a pad ring configuration for the FPGA implementation;
• partition the portion of the integrated circuit into the one or more FPGAs;
• determine pin multiplexing assignments for signals passed between FPGAs;
• define daughter cards to be inserted into a board to which the FPGAs are mounted;
• and
• generate a bitstream to program the one or more FPGAs for the implementation.