US 8,479,132 B2 · Active trace assertion based verification system

Abstract

A computer processes simulation data indicating values of circuit signals as functions of simulation time to determine whether a circuit exhibits a property defined by an assertion. The assertion expresses the property as a sequence of expressions, each a function of one or more variables, where each variable represents a value of one or more signals or a value of another sequence of expressions. The assertion statement separately defines an evaluation time for each expression, a particular simulation time at which the expression is to be evaluated. Each expression must evaluate true if the circuit has the property. The computer produces a display including a representation of each expression of the property including a separate variable symbol for each of its variables. For each expression that evaluated false, the computer identifies each variable that caused that expression to evaluate false and distinctively marks that variable's symbol relative to other variable symbols within the display. For each expression that evaluated true, the computer identifies the evaluation time contributing the fulfillment of assertion property. The computer also annotates the representation of each expression with its corresponding evaluation time and annotates each displayed variable symbol with a value of the variable it represents.

Claims34

Dependent claims

A computer implemented method for generating a display indicating whether a circuit has a property comprising:

providing an assertion based on data indicating values of signals of the circuit at a succession of simulation times, wherein the assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of simulation times at which the expression is to be evaluated,
wherein a value of each expression is a function of a value of at least one variable representing either a value of at least one signal of the circuit or a value of another separately defined sequence of expressions, and
wherein the circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time, the method comprising evaluating each expression of the first sequence by using a computer, identifying the simulation time at which the expression is first time evaluated true and, if at least one of the expressions is evaluated false, performing the further steps of:
a. displaying the representation of an expression for each of a plurality of the evaluated expressions of the first sequence, wherein the representation of the expression comprises a separate variable symbol for each of its variables;
b. annotating the displayed representation of each expression which was evaluated true with its corresponding identified simulation time at which the expression was first time evaluated true, without showing tick-by-tick evaluating steps to annotate the expression.

2 more elements

Non-transitory Computer-readable media containing a program which when read and executed by a computer causes the computer to implement a method for generating a display indicating whether a circuit has a property comprising:

providing an assertion based on data indicating values of signals of the circuit at a succession of simulation times,
wherein the assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of simulation times at which the expression is to be evaluated,
wherein a value of each expression is a function of a value of at least one variable representing either a value of at least one signal of the circuit or a value of another separately defined sequence of expressions, and
wherein the circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time,
the method comprising evaluating each expression of the first sequence by using a computer, identifying the simulation time at which the expression is first time evaluated true and, if at least one of the expressions is evaluated false, performing the further steps of:
a. displaying the representation of an expression for each of a plurality of the evaluated expressions of the first sequence, wherein the representation of the expression comprises a separate variable symbol for each of its variables;
b. annotating the displayed representation of each expression which was evaluated true with its corresponding identified simulation time at which the expression was first time evaluated true, without showing tick-by-tick evaluating steps to annotate the expression.

4 more elements

Dependencies are inferred from the claim text.

Active trace assertion based verification system

Life of this patent

Active trace assertion based verification system

Life of this patent

Abstract

Claims34