US 8,479,130 B1Granted

Method of designing integrated circuit that accounts for device aging

AssigneeFreescale Semiconductor, Inc.

InventorsZhichen Zhang, Chuanzheng Wang

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Abstract

A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.

Claims14

Dependent claims

A method of designing a semiconductor integrated circuit (‘IC’), including:

providing a library of standard cells each having respective definitions of inter-connected devices and pins for connection to other cells and/or ports, the library containing layout and performance data for respective cells;
providing a device activity file (DAF) of electrical activity of devices in the respective standard cells as a function of electrical activity at the pins of the standard cells;
providing a standard cell evolution file (SCEF) evolution of electrical characteristics of respective standard cells as a function of aging evolution of electrical characteristics of devices in the standard cells;
providing an instance activity file (IAF) simulating electrical activity at the pins of individual instances of the cells in the IC;
using said IAF and said DAF to provide a simulation of activity of said devices in the IC and consequent aging evolution of electrical characteristics of said devices;
using said SCEF and said simulation of consequent aging evolution of electrical characteristics of said devices to generate data for consequent aging evolution of electrical characteristics of said instances;
using said data for consequent aging evolution of electrical characteristics of said instances to generate data for consequent aging evolution of electrical characteristics of the IC, wherein generating data for consequent aging evolution of electrical characteristics of said instances includes generating a schematic view of aged instances corresponding to a schematic view of fresh instances and using said schematic view of the aged instances in generating data for consequent aging evolution of electrical characteristics of the IC,
wherein said generating the consequent aging evolution data is performed by a computer;
and
wherein simulating said electrical activity in said IAF includes providing numbers of electrical switching and of mark-to-space ratios at the pins of individual instances of the cells in the IC.

7 more elements

A non-transitory computer readable medium with a computer program element stored thereon that is executable by a data processor in a method of designing a semiconductor integrated circuit (IC) using a library of standard cells each having inter-connected devices and pins for connection to other cells, the library containing layout and performance data for respective cells, a device activity file (DAF) of stored electrical activity of devices in the respective standard cells as a function of electrical activity at the pins of the standard cells, a standard cell evolution file (SCEF) of stored evolution of electrical characteristics of respective standard cells as a function of aging evolution of electrical characteristics of devices in the standard cells, and an instance activity file (IAF) of simulation electrical activity at the pins of individual instances of the cells in the IC, the computer program element comprising instructions for:

using said IAF and said DAF to provide a simulation of activity of said devices in the IC and consequent aging evolution of electrical characteristics of said devices;
using said SCEF and said simulation of consequent aging evolution of electrical characteristics of said devices to generate data for consequent aging evolution of electrical characteristics of said instances;
using said data for consequent aging evolution of electrical characteristics of said instances to generate data for consequent aging evolution of electrical characteristics of the IC, wherein generating data for consequent aging evolution of electrical characteristics of said instances includes generating a schematic view of aged instances corresponding to a schematic view of fresh instances and generating data for consequent aging evolution of electrical characteristics of the IC;
and
wherein simulating said electrical activity in said instance activity file includes providing numbers of electrical switching and of mark-to-space ratios at the pins of individual instances of the cells in the IC.

2 more elements

Dependencies are inferred from the claim text.