Dynamic time domain randomization techniques for SOC and IP verification
AssigneeMarvell International Ltd.
InventorsRavishankar Kalyanaraman, Kumaril Bhatt, Nikhil Mungre
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Abstract
The present disclosure describes a memory block manager. In some aspects a request is transmitted to a model of an IP block at a randomized time and a response is received from the model of the IP block useful to characterize behavior of the IP block when fabricated. In other aspects a response to a request is transmitted to a model of an IP block at a randomized time and a communication is received from the model of the IP block useful to characterize behavior of the fabricated IP block when fabricated.
Claims20
A method comprising:
- transmitting, via a bus functional model, multiple requests to a model of an IP block at respective randomized times, each of the respective randomized times dynamically calculated on a per-transaction basis using a distributed weighted randomization effective to subject the model of the IP block to a loading condition, the bus functional model implemented by executing instructions embodied on one or more computer-readable storage devices;
- and
- receiving, via the bus functional model, multiple respective responses from the model of the IP block that characterize behavior of the IP block when fabricated and subjected to the loading condition.
A method comprising:
- transmitting, via a bus functional model, multiple responses to a model of an IP block at respective randomized times, each of the multiple responses responding to a request from the model of the IP block, each of the respective randomized times dynamically calculated on a per-transaction basis using a distributed weighted randomization effective to subject the model to a loading condition, the bus functional model implemented by executing instructions embodied on one or more computer-readable storage devices;
- and
- receiving, via the bus functional model, communication from the model of the IP block useful to characterize behavior of the IP block when fabricated and subjected to the complex loading condition.
One or more computer-readable storage devices embodying computer-executable instructions that, when executed, implement a bus functional model to:
- query a delay model for a delay specification, the delay specification having a distributed weighted randomization constraint, the delay model separate from the bus functional model;
- transmit, to a model of an IP block, multiple requests at respective randomized times effective to subject the model of the IP block to a loading condition, each of the respective randomized times dynamically calculated on a per-transaction basis using the delay specification;
- and
- receive, from the model of the IP block, multiple respective responses useful to characterize behavior of the IP block when fabricated and subjected to the loading condition.
Dependencies are inferred from the claim text.