Technique for honoring multi-cycle path semantics in RTL simulation
AssigneeSynopsys, Inc.
InventorsKaushik De, Badri P. Gopalan, Dhiraj Goswami
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Abstract
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.
Claims21
A method for enhancing register transfer level (RTL) simulation, the method comprising:
- accessing an RTL file and a sideband file for a design;
- identifying design constraints in the sideband file, the design constraints including multi-cycle paths;
- using a computer, modifying the design by duplicating portions of the multi-cycle paths to create modified multi-cycle paths, inserting delays in the modified multi-cycle paths, and cutting the multi-cycle paths from their sources;
- and
- simulating the modified design during the RTL simulation.
A computer-readable medium storing computer-executable instructions for enhancing register transfer level (RTL) simulation, which when executed by a computer performs steps comprising:
- accessing an RTL file and a sideband file for a design;
- identifying design constraints in the sideband file, the design constraints including multi-cycle paths;
- modifying the design by duplicating portions of the multi-cycle paths to create modified multi-cycle paths, inserting delays in the modified multi-cycle paths, and cutting the multi-cycle paths from their sources;
- and
- simulating the modified design during the RTL simulation.
A system for enhancing register transfer level (RTL) simulation, the system including a processor configured to perform steps comprising:
- accessing an RTL file and a sideband file for a design;
- identifying design constraints in the sideband file, the design constraints including multi-cycle paths;
- using a computer, modifying the design by duplicating portions of the multi-cycle paths to create modified multi-cycle paths, inserting delays in the modified multi-cycle paths, and cutting the multi-cycle paths from their sources;
- and
- simulating the modified design during the RTL simulation.
Dependencies are inferred from the claim text.