Memory system with error correction decoder architecture having reduced latency and increased throughput

In a memory system, a method of processing data received by a memory controller from a memory device, the method comprising:

• receiving data from a memory device;
• demultiplexing the received data into a first set of data and a second set of data;
• storing the first set of data into a first buffer memory;
• determining whether the first set of data includes any errors, while storing the second set of data into a second buffer memory;
• multiplexing the first set of data from the first buffer memory and the second set of data from the second memory buffer;
• providing the multiplexed data to an error corrector;
• and
• correcting one or more errors in the first set of data with the error corrector while determining whether the second set of data includes any errors.