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US 8,479,083 B2Granted
Flash memory devices having multi-bit memory cells therein with improved read reliability
AssigneeSamsung Electronics Co., Ltd.
InventorsDonghyuk Chae, Jinman Han
Life of this patent
Estimating the term…
Abstract
Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.
Claims16
A flash memory device comprising:
- a memory cell array including a plurality of memory cells;
- a control logic configured to control a read operation on the memory cells;
- a page buffer circuit configured to sense hard decision data and a plurality of soft decision data from each of a plurality of selected memory cells in response to the control of the control logic and output the sensed hard decision data and the plurality of soft decision data as a read result;
- and
- a voltage generator configured to generate a plurality of read voltages for reading the hard decision data and the plurality of soft decision data in response to the control of the control logic;
- wherein the read result includes the hard decision data of 1 bit and the soft decision data of j bits where j is a positive integer.
3 more elements
A flash memory device comprising:
- a memory cell array including a plurality of memory cells;
- a control logic configured to control a read operation on the memory cells;
- a page buffer circuit configured to sense hard decision data and a plurality of soft decision data from each of a plurality of selected memory cells in response to the control of the control logic and output the sensed hard decision data and the plurality of soft decision data as a read result;
- and
- a voltage generator configured to generate a plurality of read voltages for reading the hard decision data and the plurality of soft decision data in response to the control of the control logic;
- wherein the soft decision data included in the read result are outputted in the format sensed by the page buffer circuit, or are encoded and outputted as reliability data;
- and
- wherein the reliability data are encoded in the page buffer circuit.
5 more elements
A flash memory device comprising:
- a memory cell array including a plurality of memory cells;
- a control logic configured to control a read operation on the memory cells;
- a page buffer circuit configured to sense hard decision data and a plurality of soft decision data from each of a plurality of selected memory cells in response to the control of the control logic and output the sensed hard decision data and the plurality of soft decision data as a read result;
- and
- a voltage generator configured to generate a plurality of read voltages for reading the hard decision data and the plurality of soft decision data in response to the control of the control logic;
- wherein the soft decision data included in the read result are outputted in the format sensed by the page buffer circuit, or are encoded and outputted as reliability data;
- and
- wherein the read result includes the hard decision data of 1 bit and the reliability data of i bits where i is a positive integer smaller than j.
5 more elements
A flash memory device comprising:
- a memory cell array including a plurality of memory cells;
- a control logic configured to control a read operation on the memory cells;
- a page buffer circuit configured to sense hard decision data and a plurality of soft decision data from each of a plurality of selected memory cells in response to the control of the control logic and output the sensed hard decision data and the plurality of soft decision data as a read result;
- and
- a voltage generator configured to generate a plurality of read voltages for reading the hard decision data and the plurality of soft decision data in response to the control of the control logic;
- wherein the soft decision data included in the read result are outputted in the format sensed by the page buffer circuit, or are encoded and outputted as reliability data;
- and
- wherein the page buffer circuit includes a plurality of page buffers corresponding respectively to the selected memory cells, and each of the page buffers includes a plurality of first type latches configured to encode the reliability data by a latched value toggled in response to a value of the soft decision data and a second type latch configured to latch the hard decision data.
5 more elements
A read method of a flash memory device, comprising:
- generating a plurality of variable read voltages and a reference voltage for reading hard decision data from each of selected memory cells;
- sensing the hard decision data and a plurality of soft decision data by applying the reference voltage and the variable read voltages to the selected memory cells;
- and
- outputting the sensed hard decision data and soft decision data as a read result, wherein the soft decision data are outputted in the sensed format, or are encoded and outputted as reliability data;
- wherein the reliability data are encoded in a page buffer circuit.
2 more elements
A read method of a flash memory device, comprising:
- generating a plurality of variable read voltages and a reference voltage for reading hard decision data from each of selected memory cells;
- sensing the hard decision data and a plurality of soft decision data by applying the reference voltage and the variable read voltages to the selected memory cells;
- and
- outputting the sensed hard decision data and soft decision data as a read result, wherein the soft decision data are outputted in the sensed format, or are encoded and outputted as reliability data;
- wherein the read result includes the hard decision data of 1 bit and the soft decision data of j bits where j is a positive integer.
2 more elements
A read method of a flash memory device, comprising:
- generating a plurality of variable read voltages and a reference voltage for reading hard decision data from each of selected memory cells;
- sensing the hard decision data and a plurality of soft decision data by applying the reference voltage and the variable read voltages to the selected memory cells;
- and
- outputting the sensed hard decision data and soft decision data as a read result, wherein the soft decision data are outputted in the sensed format, or are encoded and outputted as reliability data;
- wherein the read result includes the hard decision data of 1 bit and the reliability data of i bits where i is a positive integer smaller than j.
2 more elements
A read method of a flash memory device, comprising:
- generating a plurality of variable read voltages and a reference voltage for reading hard decision data from each of selected memory cells;
- sensing the hard decision data and a plurality of soft decision data by applying the reference voltage and the variable read voltages to the selected memory cells;
- and
- outputting the sensed hard decision data and soft decision data as a read result, wherein the soft decision data are outputted in the sensed format, or are encoded and outputted as reliability data;
- wherein the reliability data are encoded by the toggled latched values of two or more latches of page buffers corresponding respectively to the selected memory cells, in response to the values of the soft decision data corresponding respectively to the selected memory cells.
2 more elements
Dependencies are inferred from the claim text.