Memory device and bit error detection method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsShea-Yun Lee, Dong-Hyun Song, Jang-Hwan Kim, Sang-Lyul Min
Life of this patent
Estimating the term…
Abstract
A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.
Claims20
A memory device comprising:
- a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells;
- and
- an error correction code (ECC) circuit generating an ECC code corresponding to the data and detecting and correcting an error of the data by means of the ECC code during a read operation,
- wherein the CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects an error of the data not corrected by the ECC circuit according to a comparison of the read CRC code and the write CRC code.
A memory device comprising:
- a cyclic redundancy check (CRC) circuit generating a write CRC code corresponding to data to be stored in memory cells;
- a first error correction code (ECC) circuit generating a first ECC code corresponding to the data and detecting and correcting an error of the data by means of the first ECC code during a read operation;
- and
- a second ECC circuit generating a second ECC code corresponding to the write CRC code and detecting and correcting an error of the write CRC code by means of the second ECC code during the read operation,
- wherein the CRC circuit generates a read CRC code corresponding to data corrected by the first ECC circuit during the read operation, and detects an error of the data not corrected by the ECC circuit according to a comparison of the read CRC code and the write CRC code corrected by the second ECC circuit.
A method of detecting an error in a memory device, comprising:
- generating, by an ECC circuit, error correction code (ECC) and cyclic redundancy check (CRC) codes corresponding to data to be stored in memory cells;
- storing the data in the memory cells;
- generating corrected data by correcting an error for the data stored in the memory cells by utilizing the ECC code;
- generating, by a CRC circuit, a read CRC code corresponding to the corrected data;
- and
- detecting an error of the corrected data not corrected by the ECC circuit according to a comparison of the read CRC code to the write CRC code.
A method of detecting an error in a memory device, comprising:
- generating, by a CRC circuit, a write cyclic redundancy check (CRC) code corresponding to data to be stored in memory cells;
- generating, by a first ECC circuit, a first error correction code (ECC) code corresponding to the data to be stored in the memory cells, and a second ECC code, by a second ECC circuit, corresponding to the write CRC code;
- programming the data, the write CRC code, and the first and second ECC codes into the memory cells;
- generating corrected data by correcting an error of the data by means of the first ECC code
- generating corrected write CRC code by correcting an error of the write CRC code by means of the second ECC code;
- generating a read CRC code corresponding to the corrected data;
- and
- detecting, by the CRC circuit, an error of the corrected data not corrected by the ECC circuits according to a comparison of the read CRC code and the corrected write CRC code.
Dependencies are inferred from the claim text.