Integrated circuit arrangement for test inputs
AssigneeInternational Business Machines Corporation
InventorsUlrich Baur, Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching L. Tong, Tobias Webel
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Abstract
An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
Claims16
An integrated circuit chip including:
- a mainline function logic path communicatively connected to a first input/output (I/O) pin;
- a test logic path;
- a latch disposed between the test logic path and the first I/O pin to form a communicative connection therebetween;
- and
- a second I/O pin communicatively connected to the latch and to the test logic path, the second I/O pin operative to send a signal operative to change a state of the latch.
A method for operating an integrated circuit chip, the method including:
- sending a first signal from a first input/output (I/O) pin to a latch and to a test logic path, the first signal operative to change a state of the latch from an open state to a closed state;
- and
- sending a second signal from a second I/O pin to the test logic path, wherein the second signal follows a conductive path through the latch in the closed state to the test logic path.
Dependencies are inferred from the claim text.