Decoded register outputs enabling test clock to selected asynchronous domains

An integrated circuit comprising:

• A. logic circuitry clock domains, each clock domain having a separate clock input;
• B. function clock circuits, each function clock circuit having a function clock output and the function clock circuits being asynchronous with one another;
• C. a test clock lead, a scan enable lead, and a select lead;
• D. a shift register having a serial input, a serial output, and parallel outputs;
• E. decoder circuitry having parallel inputs connected to the parallel outputs of the shift register and having enable outputs, there being one enable output for each clock domain;
• F. clock gating circuitry for each of the logic circuitry clock domains, each clock gating circuitry having a clock input coupled to the test clock lead, a scan enable input connected to the scan enable lead, an enable input connected to one of the enable outputs of the decoder circuitry, and a gated clock output;
• and
• G. multiplexer circuitry for each of the logic circuitry clock domains, each multiplexer circuitry having a first input connected to one of the gated clock outputs, a second input connected to one of the function clock outputs, a control input connected to the select lead, and an output connected to the clock input of one of the logic circuit clock domains.