Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

A non-transitory computer-readable medium comprising computer instructions that, when run on a computer, perform a process for testing of an integrated circuit design, the process comprising:

• receiving scan inputs and mapping the scan inputs to a plurality of scan chains and a plurality of cyclical cache chains;
• receiving first outputs of the plurality of scan chains and second outputs of the plurality of cyclical cache chains, and generating scan outputs from the first and second outputs;
• inverting one or more values from the cyclical cache chains, the inverting values being a subset of the scan inputs;
• and
• selecting between a linear mode and a cyclical mode,
• wherein in the linear mode, only top level scan inputs are mapped to the plurality of scan chains, the top level scan inputs including any external source scan inputs, and
• wherein in the cyclical mode, outputs of the plurality of cyclical cache chains and the top level scan inputs are mapped to the plurality of scan chains.

A test architecture for testing of an integrated circuit design, the test architecture comprising:

• a plurality of scan chains;
• a plurality of cyclical cache chains;
• means for receiving scan inputs and mapping the scan inputs to the plurality of scan chains and the plurality of cyclical cache chains;
• means for receiving outputs of the plurality of scan chains and the plurality of cyclical cache chains, and generating scan outputs;
• means for inverting one or more values from the cyclical cache chains, the means for inverting generating a subset of the scan inputs for the means for receiving outputs;
• and
• means for selecting between a linear mode and a cyclical mode,
• wherein in the linear mode, only top level scan inputs are mapped to the scan chains, the top level scan inputs including any external source scan inputs, and
• wherein in the cyclical mode, the outputs of the plurality of cyclical cache chains and the top level scan inputs are mapped to the scan chains.

A method of testing of an integrated circuit design, the method comprising:

• receiving scan inputs and mapping the scan inputs to a plurality of scan chains and a plurality of cyclical cache chains;
• receiving first outputs of the plurality of scan chains and second outputs of the plurality of cyclical cache chains, and generating scan outputs from the first and second outputs;
• inverting one or more values from the cyclical cache chains, the inverting values being a subset of the scan inputs;
• and
• using a computer, selecting between a linear mode and a cyclical mode,
• wherein in the linear mode, only top level scan inputs are mapped to the plurality of scan chains, the top level scan inputs including any external source scan inputs, and
• wherein in the cyclical mode, outputs of the plurality of cyclical cache chains and the top level scan inputs are mapped to the plurality of scan chains.

A method of testing of an integrated circuit design, the method comprising:

• receiving scan inputs and mapping the scan inputs to a plurality of scan chains and a plurality of cyclical cache chains;
• receiving first outputs of the plurality of scan chains and second outputs of the plurality of cyclical cache chains, and generating scan outputs from the first and second outputs;
• processing one or more values from the plurality of cyclical cache chains, the processed values being a subset of the scan inputs;
• and
• using a computer, selecting between a linear mode and a cyclical mode,
• wherein in the linear mode, only first level scan inputs are mapped to the plurality of scan chains, the first level scan inputs not including internally-generated scan inputs, and
• wherein in the cyclical mode, outputs of the plurality of cyclical cache chains and the first level scan inputs are mapped to the plurality of scan chains.