Failure analyzing device and failure analyzing method

A failure analyzing device, comprising:

• a dividing unit that receives a fail bit map where non-failure/failure information of individual cells of a semiconductor memory is arranged in order of physical addresses corresponding to a physical layout of the memory cells, and divides the fail bit map for each layer;
• a first extracting unit that extracts a failed cell common to layers of a predetermined number or more, from the divided fail bit maps, and generates a layer common fail bit map;
• a second extracting unit that extracts a unique failed cell of each layer from the fail bit map of each layer and generates a layer unique fail bit map;
• a classifying unit that classifies a failure type in the layer common fail bit map and classifies a failure type in the layer unique fail bit map corresponding to each layer;
• a storage unit that stores a table where a correspondence relationship between a name of the failure type in the layer common fail bit map and a three-dimensional failure type name is defined;
• a converting unit that refers to the table, converts a failure name of a classification result of the layer common fail bit map based on the classifying unit into the three-dimensional failure type name, and generates a layer common failure classification result;
• and
• a synthesizing unit that synthesizes the classification result of the layer unique fail bit map based on the classifying unit and the layer common failure classification result.

A failure analyzing method, comprising:

• receiving a fail bit map where non-failure/failure information of individual cells of a semiconductor memory is arranged in order of physical addresses corresponding to a physical layout of the memory cells;
• dividing the fail bit map for each layer;
• classifying a failure type in the fail bit map corresponding to each layer;
• and
• determining whether a classification result of the failure type is matched with a rule where the failed cells of different layers are combined as the same failure type and grouping the matched classification result,
• wherein the rule includes a base point failure, an association failure becoming a combination object of the base point failure, a combination condition defining a relationship between the base point failure and the association failure, and a combination failure name, and
• the grouping of the classification result includes extracting the base point failure from the classification result of one layer, extracting the association failure matched with the combination condition, from the classification results of the other layers, and grouping the extracted base point failure and association failure and providing the combination failure name.

A failure analyzing method, comprising:

• receiving a fail bit map where non-failure/failure information of individual cells of a semiconductor memory is arranged in order of physical addresses corresponding to a physical layout of the memory cells;
• dividing the fail bit map for each layer;
• extracting a failed cell common to layers of the predetermined number or more, from the divided fail bit maps, and generating a layer common fail bit map;
• extracting a unique failed cell of each layer from the fail bit map of each layer and generating a layer unique fail bit map;
• classifying a failure type in the layer common fail bit map;
• classifying a failure type in the layer unique fail bit map corresponding to each layer;
• referring to a table where a correspondence relationship between a name of the failure type in the layer common fail bit map and a three-dimensional failure type name is defined, converting a failure name of a classification result of the failure type in the layer common fail bit map into the three-dimensional failure type name, and generating a layer common failure classification result;
• and
• synthesizing the classification result of the failure type in the layer unique fail bit map and the layer common failure classification result.