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US 8,479,053 B2Granted
Processor with last branch record register storing transaction indicator
AssigneeIntel Corporation
InventorsRavi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
Life of this patent
Estimating the term…
Abstract
In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
Claims22
An apparatus comprising:
- a processor including an execution unit and at least one last branch record (LBR) register to store at least one of source and destination address information of a branch taken during program execution, the at least one LBR register further including a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction.
A method comprising:
- inserting branch address information into a last branch record (LBR) entry of a processor when a branch is taken during program execution;
- writing a transaction indicator of the LBR entry if the branch is taken during execution of a transactional memory (TM) transaction, and otherwise not writing the transaction indicator;
- and
- writing an abort indicator of the LBR entry if the branch occurs after an abort of the TM transaction, and otherwise not writing the abort indicator.
1 more element
A system comprising:
- a processor including an execution unit and a plurality of last branch record (LBR) register pairs each to store source and destination address information of a branch taken during program execution, each of the LBR register pairs further including a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction and an abort indicator to indicate whether an abort of the TM transaction occurred prior to when the branch was taken;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.