Transaction-level lockstep
AssigneeXilinx, Inc.
InventorsPhilip B. James-Roxby, Ralph D. Wittig
Life of this patent
Estimating the term…
Abstract
An embodiment of a method for a high-assurance operation is disclosed. For this embodiment of the method, a first processor and a second processor are clocked for lockstep operation. A first physical address and a first transaction request are provided to a shared bus from the first processor. A second physical address and a second transaction request are provided to the shared bus from the second processor. The first physical address, the first transaction request, the second physical address, and the second transaction request are passed to a proxy device coupled to the shared bus. The first processor and the second processor are proxy served by the proxy device including generation of a third transaction request and a third physical address by the proxy device.
Claims20
A method for a high-assurance operation, comprising:
- clocking a first processor and a second processor for lockstep operation on a cycle-by-cycle basis;
- providing to a shared bus a first physical address and a first transaction request from the first processor;
- providing to the shared bus a second physical address and a second transaction request from the second processor;
- passing the first physical address, the first transaction request, the second physical address, and the second transaction request to a proxy device coupled to the shared bus;
- and
- proxy serving the first processor and the second processor by the proxy device including generation of a third transaction request and a third physical address by the proxy device.
A system for high-assurance operation, comprising:
- a first processor and a second processor coupled to a shared bus;
- wherein the first processor and the second processor are each coupled to receive a same clock signal;
- wherein the first processor and the second processor are clocked for lockstep operation on a cycle-by-cycle basis of the clock signal;
- and
- a proxy device coupled to the shared bus to receive physical addresses and transaction requests from the first processor and the second processor;
- wherein the proxy device is configured to:
- compare address information from the first processor and the second processor;
- compare transaction information from the first processor and the second processor;
- and
- generate a proxy physical address and a proxy transaction request responsive to the address information and the transaction information being for a transaction-level lockstep operation.
A method for proxy servicing, comprising:
- programming programmable resources to provide a proxy device;
- clocking a first processor and a second processor with a same clock signal;
- wherein the first processor and the second processor are clocked for lockstep operation on a cycle-by-cycle basis of the clock signal;
- providing a first physical address and a first instruction from the first processor to a first interface of the proxy device;
- providing a second physical address and a second instruction from the second processor to a second interface of the proxy device;
- determining by the proxy device for a transaction-level lockstep operation that:
- the first physical address and the second physical address are for a same memory location associated with a memory device or a memory mapped peripheral device;
- and
- the first instruction and the second instruction are for a same action;
- and
- generating by the proxy device for the proxy servicing:
- a third instruction as a substitute for the first instruction and the second instruction;
- and
- a third physical address as a substitute for the first physical address and the second physical address.
Dependencies are inferred from the claim text.