Controlling the power usage of a computer
AssigneeHewlett-Packard Development Company, L.P.
InventorsScott P. Faasse, Alan L. Goodrum
Life of this patent
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Abstract
A method and apparatus for controlling the power usage of a processor is disclosed. The power usage of the processor is monitored. When the power usage of the processor exceeds a threshold power usage value, the power used by the processor is reduced or limited. A processor utilization value is also monitored. When the processor utilization value is above a threshold utilization value, the processor is ramped to a higher performance state. When power to the processor is being limited, a first rate is used to ramp the processor to the higher performance state. When power to the processor is not being limited, then a second rate, different from the first rate, is used to ramp the processor to the higher performance state.
Claims14
A method for controlling power usage of a processor, comprising:
- monitoring the power usage of the processor;
- limiting the power used by the processor when the power usage of the processor exceeds a threshold power usage value;
- monitoring processor utilization and ramping the processor to a higher performance state when the processor utilization is above a threshold utilization;
- when power to the processor is being limited then using a first rate for ramping the processor to the higher performance state;
- when power to the processor is not being limited then using a second rate, different from the first rate, for ramping the processor to the higher performance state.
The method for controlling power usage of a processor of claim further comprising:
- ramping the processor to a lower performance state when the processor utilization is below a second threshold utilization;
- when power to the processor is being limited then using a third rate for ramping the processor to the lower performance state;
- when power to the processor is not being limited then using a fourth rate, different from the third rate, for ramping the processor to the lower performance state.
A computer system, comprising:
- a processor operable at a plurality of power levels, the processor capable of storing a processor utilization value, the processor running a performance management module;
- a management controller coupled to the processor, the management controller running a power capping module
- the power capping module monitoring the power usage of the processor;
- the power capping module reducing power to the processor when the power usage of the processor exceeds a threshold power usage value;
- the performance management module monitoring the processor utilization value and ramping the processor to a higher performance state when the processor utilization value is above a threshold utilization value;
- when power to the processor is being limited by the power capping module then the performance management module will use a first rate for ramping the processor to a higher performance state;
- when power to the processor is not being limited by the power capping module then the performance management module will use a second rate, different from the first rate, for ramping the processor to a higher performance state.
A computer system, comprising:
- a plurality of processors, each processor operable at a plurality of power levels, each processor capable of storing a processor utilization value;
- at least one management controller coupled to the plurality of processors, the at least one management controller running a power capping module;
- a plurality of micro-controllers, wherein each of the plurality of micro-controllers runs an instantiation of a performance management module;
- the power capping module monitoring the power usage of the plurality of processors;
- the power capping module reducing power to at least one of the plurality of processors when the power usage of the plurality of processor exceeds a threshold power usage value;
- each of the plurality of performance management modules monitoring the processor utilization value for at least one of the plurality of processor and ramping the at least one of the plurality of processor to a higher performance state when the corresponding processor utilization value is above a threshold utilization value;
- when power to one of the plurality of processors is being limited by the power capping module then each of the plurality of performance management modules will use a first rate for ramping each of the plurality of processors to a higher performance state;
- when power to any of the plurality of processors is not being limited by the power capping module then each of the plurality of performance management modules will use a second rate, different from the first rate, for ramping each of the plurality of processors to a higher performance state.
Dependencies are inferred from the claim text.