Power management of components having clock processing circuits
AssigneeAltera Corporation
InventorDaniel J. Allen
Life of this patent
Estimating the term…
Abstract
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal.
Claims22
A method for managing power consumption of a component that uses a processed clock signal produced by a clock processing circuit, comprising:
- changing a frequency of a clock signal supplied as input to the clock processing circuit in order to manage power consumption of the component;
- and
- generating digital period values each of which describes a period of the clock signal at a cycle of the clock signal, wherein the clock signal is produced by a digital waveform synthesizer that is capable of changing a frequency of the clock signal every clock cycle in response to a digital period value received as an input thereto;
- wherein changing comprises changing the digital period values supplied as input to the digital waveform synthesizer in order to reduce a time interval required for a transition of the processed clock signal from a first frequency to a second frequency.
A system comprising:
- a clock circuit that is configured to generate a clock signal at a frequency, wherein the clock circuit comprises a digital waveform synthesizer circuit that generates the clock signal based on digital period values supplied as input to the digital waveform synthesizer circuit, wherein each digital period value describes a period of the clock signal at a cycle of the clock signal, and wherein the digital waveform synthesizer circuit is capable of changing the frequency of the clock signal every clock cycle in response to corresponding digital period values received as input thereto;
- a clock processing circuit that receives as input the clock signal and produces a processed clock signal for use by a component;
- and
- a control circuit configured to change the frequency of the clock signal in order to manage power consumption of the component, wherein the control circuit supplies digital period values to the digital waveform synthesizer circuit in order to change the frequency of the clock signal.
An apparatus for managing power of a component that uses a processed clock signal produced by a clock processing circuit, comprising:
- a clock circuit configured to generate a clock signal at a frequency, wherein the clock circuit comprises a digital waveform synthesizer circuit that generates the clock signal based on digital period values supplied as input to the digital waveform synthesizer circuit, wherein each digital period value describes a period of the clock signal at a cycle of the clock signal, and wherein the digital waveform synthesizer circuit is capable of changing the frequency of the clock signal every clock cycle in response to corresponding digital period values received as input thereto;
- and
- a control circuit configured to control the clock circuit to change the frequency of the clock signal in order to manage power consumed by the component, wherein the control circuit supplies digital period values to the digital waveform synthesizer circuit in order to change the frequency of the clock signal.
Dependencies are inferred from the claim text.