Methods and apparatuses for reducing step loads of processors

A system, comprising:

• a plurality of cores;
• a plurality of core controllers each associated with one of the plurality of cores and to control a power level of the corresponding core;
• and
• a socket controller to monitor requests of the plurality of core controllers for changes to power levels of the plurality of cores, wherein the socket controller is to maintain an average power consumption, wherein the socket controller is to determine a minimum amount of time required before allowing one of the plurality of core controllers to cause a corresponding core to change from a first power level to a second power level.

A method comprising:

• examining a plurality of instructions to be processed by a processor to determine types of instructions in the plurality of instructions;
• calculating a quantity of power to be consumed by the processor in a period of execution based on the types of instructions;
• limiting execution of the processor in the execution period to a first subset of instructions of a first power level, and thereafter allowing a second subset of instructions of a second power level to be executed;
• and
• adjusting a created amount of artificial activity to maintain a minimum power floor, and creating the amount of artificial activity by one of turning on a clock to keep clock switching power constant, changing data patterns, and using power resistors.