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US 8,478,969 B2Granted
Performing a multiply-multiply-accumulate instruction
AssigneeIntel Corporation
InventorEric S. Sprangle
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a processor having a plurality of execution units, at least one of the execution units including a circuit comprising:
- a first multiplier to multiply a first reference value with a first coefficient to obtain a first product;
- a second multiplier to multiply a second reference value with a second coefficient to obtain a second product;
- a first adder to combine the first and second products to obtain a first sum;
- a second adder to combine the first sum and a third term to obtain a base value;
- a third level of adders each to combine the base value with one of a plurality of representations of the first coefficient to obtain a first sum set;
- and
- a fourth level of adders each to combine the first sum set with one of a plurality of representations of the second coefficient to obtain a second sum set, wherein the circuit is to populate a vector destination storage having a plurality of locations each to store an output of one of the third and fourth levels of adders.
5 more elements
A method comprising:
- receiving a dual multiply-add instruction in a front end unit of a processor;
- decoding the dual multiply-add instruction and sending the decoded instruction and operands therefore to an execution unit of the processor;
- and
- executing the decoded instruction in the execution unit, including performing a plurality of multiplication operations, first and second additions to obtain a base value, manipulating the base value in a first set of adders to obtain intermediate sum values, manipulating each of the intermediate sum values in a second set of adders to obtain final sum values, and storing at least the intermediate sum values and final sum values in a destination storage.
1 more element
A system comprising:
- a processor having a plurality of execution units, at least one of the execution units including a circuit comprising a multiply-accumulate (MAC) unit including a plurality of multipliers and a plurality of adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to a value for a pixel of a pixel block, wherein a number of the plurality of adders exceeds a number of pixels in the pixel block;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.