Stall propagation in a processing system with interspersed processors and communicaton elements

A method for operating a multiprocessor system, the method comprising:

• executing at least one program on a plurality of processors;
• wherein said executing comprises:
• at least a subset of the plurality of processors communicating with each other through a plurality of dynamically configurable communication elements, wherein each of at least a portion of the dynamically configurable communication elements comprises a memory and a routing engine, and wherein at least some of the processors and at least some of the dynamically configurable communication elements are coupled together in an interspersed arrangement;
• a source device initiating transfer of a data item through an intermediate subset of the dynamically configurable communication elements to a destination device;
• wherein the source device corresponds to a particular one of the processors, a particular one of the dynamically configurable communication elements, or an input/output device;
• wherein the destination device corresponds to a different one of the processors, a different one of the dynamically configurable communication elements, or a different input/output device;
• in response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device propagating stalling information through one or more of the intermediate subset towards the source device;
• in response to receiving the stalling information, at least one of the intermediate subset buffering all or part of the data item.

A method of manufacturing an integrated circuit, the method comprising:

• fabricating a unit comprising a processor and a dynamically configurable communication element, wherein the dynamically configurable communication element comprises a memory and a routing engine;
• and
• placing and interconnecting a plurality of the units on a substrate, wherein processors and dynamically configurable communication elements of at least some of the units are coupled together in an interspersed arrangement;
• wherein a source device is configurable to transfer a data item through an intermediate subset of the dynamically configurable communication elements to a destination device;
• wherein the source device corresponds to a particular one of the processors, a particular one of the dynamically configurable communication elements, or an input/output device;
• wherein the destination device corresponds to a different one of the processors, a different one of the dynamically configurable communication elements, or a different input/output device;
• wherein, in response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device;
• wherein in response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.