Method and system for local data sharing
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael Mantor, Michael Mang, Karl Mann
Life of this patent
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Abstract
Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path.
Claims18
A device, comprising:
- an input queue coupled to a conflict state machine;
- an output queue;
- an address generation unit configured to generate a plurality of memory addresses;
- and
- an atomic logic and bypass unit associated with the address generation unit configured to perform atomic operations;
- wherein the conflict state machine resolves memory addressing conflicts based on the plurality of memory addresses.
A method comprising:
- analyzing memory addresses for a plurality of threads;
- checking one or more bits of the memory addresses to determine mapping to one or more memory banks;
- scheduling access to the one or more memory banks;
- and
- stalling input from a first processor to receive a first memory address of the memory addresses from a second processor.
A non-transitory computer-readable storage device having computer-executable instructions stored thereon, execution of which, by a computing device, causes the computing device to perform operations comprising:
- analyzing memory addresses for a plurality of threads;
- checking one or more bits of the memory addresses to determine mapping to one or more memory banks;
- scheduling access to the one or more memory banks;
- and
- stalling input from a first processor to receive a first memory address of the memory addresses from a second processor.
A method comprising:
- analyzing memory addresses of a plurality of threads;
- checking respective bits of the memory addresses to determine mapping to one or more memory banks;
- scheduling access to the memory banks;
- modifying the memory addresses to generate offset addresses;
- receiving a base address and a stride value;
- and
- computing a relative read address using the base address and the stride value;
- wherein the memory banks are accessed by bypassing an input queue and output queue.
A computer-readable storage device having computer-executable instructions stored thereon, execution of which, by a computing device, causes the computing device to perform operations comprising:
- analyzing memory addresses of a plurality of threads;
- checking respective bits of the memory addresses to determine mapping to one or more memory banks;
- and
- scheduling access to the memory banks;
- modifying the memory addresses to offset addresses;
- receiving a base address and a stride value;
- and
- computing a relative read address using the base address and the stride value;
- wherein the memory banks are accessed by bypassing an input queue and output queue.
Dependencies are inferred from the claim text.