Method and apparatus for reducing processor cache pollution caused by aggressive prefetching
AssigneeAdvanced Micro Devices, Inc.
InventorPatrick Conway
Life of this patent
Estimating the term…
Abstract
A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
Claims19
A method for controlling a first and second cache, comprising:
- receiving a cache entry in the first cache;
- identifying the received cache entry as having an untouched status;
- updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry;
- casting out the cache entry according to a preselected cache line replacement algorithm;
- and
- controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
A memory system, comprising:
- a first-level cache;
- a second-level cache;
- a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry, and casting out the cache entry according to a preselected cache line replacement algorithm;
- and
- a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
A microprocessor, comprising:
- a core;
- a first-level cache;
- a second-level cache;
- a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry from the core, and casting out the cache entry according to a preselected cache line replacement algorithm;
- and
- a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a memory system, comprising:
- a first-level cache;
- a second-level cache;
- a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry, and casting out the cache entry according to a preselected cache line replacement algorithm;
- and
- a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
Dependencies are inferred from the claim text.