Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses

A computer-implemented method of testing a design for an instruction fetch unit (IFU) of a microprocessor, comprising:

• supplying a sequence of instruction addresses to an IFU model which represents the IFU design, wherein the instruction addresses correspond to program instructions provided by a memory hierarchy which is external to the IFU model, and the IFU model includes an instruction cache and a plurality of address registers which are pipelined such that a first one of the address registers is designated to provide a next address to be fetched;
• fetching one or more of the program instructions according to the instruction address sequence from the external memory hierarchy to the IFU model;
• detecting that a current state of the IFU model includes an outstanding fetch request for a cache line which is in the process of being delivered to the instruction cache;
• automatically modifying the instruction address sequence responsive to said detecting without violating any rules of the microprocessor architecture by sending a flush signal to the IFU model and overwriting the first address register with a selected address, wherein the selected address is contained in the cache line;
• and
• fetching a program instruction corresponding to the selected address from the external memory hierarchy to the IFU model.