Controlling data stream interruptions on a shared interface
AssigneeInternational Business Machines Corporation
InventorsGarrett M. Drapala, Kenneth D. Klapproth, Robert J. Sonnelitter, III, Craig R. Walters
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Abstract
A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.
Claims16
A computer implemented method for controlling data stream interruptions on a shared bus, the method comprising:
- receiving a first request to transfer data,
- determining high priority data components and low priority data components for the first request, the high priority data components comprising a first portion of a cache line, and the low priority data components comprising a second portion of the cache line;
- transferring the high priority data components without interruptions;
- based on receiving further requests while transferring the high priority data components, rejecting the further requests;
- based on the transferring of the high priority data components being complete for the first request, transferring the low priority data components of the first request;
- and
- based on receiving other requests while transferring the low priority data components, allowing the other requests to interrupt the transferring of the low priority data up to a maximum allowed number of interruptions, the maximum allowed number of interruptions being based on a number of chip-to-chip interfaces for the first request.
An arbiter configured to control data stream interruptions on a shared bus, comprising:
- an input and an output for receiving and sending;
- logic gates configured to receive a first request to transfer data via the input,
- wherein the logic gates are configured to determine high priority data components and low priority data components for the first request, the high priority data components comprising a first portion of a cache line, and the low priority data components comprising a second portion of the cache line;
- wherein the logic gates are configured to transfer the high priority data components without interruptions via the output;
- wherein based on receiving further requests while transferring the high priority data components via the input, the logic gates are configured to reject the further requests;
- wherein based on the transferring of the high priority data components being complete for the first request, the logic gates are configured to transfer the low priority data components of the first request;
- and
- based on receiving other requests while transferring the low priority data components, allowing the other requests to interrupt the transferring of the low priority data up to a maximum allowed number of interruptions, the maximum allowed number of interruptions being based on a number of chip-to-chip interfaces for the first request.
A computer implemented method for controlling data stream interruptions on a shared bus, the method comprising:
- receiving a request to transfer data by an arbiter;
- transferring high priority data components of the request, the high priority data components comprising a first portion of a cache line;
- allowing the transfer of the high priority data components to be uninterrupted by other requests received at the arbiter;
- based on the transferring of the high priority data components being complete for the request, transferring low priority data components of the request the low priority data components comprising a second portion of the cache line;
- and
- based on receiving other requests while transferring the low priority data components, allowing the other requests to interrupt the transferring of the low priority data up to a maximum allowed number of interruptions, the maximum allowed number of interruptions being based on a number of chip-to-chip interfaces for the first request.
Dependencies are inferred from the claim text.