Automatic anomaly detection for HW debug

A computer system for anomaly detection in an electronic design, the system comprising:

• a non-transitory machine-readable storage medium;
• one or more processors coupled to said storage medium;
• and
• computer code stored in said storage medium wherein said computer code, when retrieved from said storage medium and executed by said one or more processor, results in:
• receiving, from the computer-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, wherein the successful simulation test is a test of the electronic system by simulation that indicates the electronic system passing the test, and each of the plurality of entries includes at least information about simulation time and information from an output electronic waveform description or an output text log file;
• determining, with one or more of the computer processors, time sequence relationship between pairs of entries selected from the plurality of entries;
• identifying, with one or more of the computer processors, allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship from the successful simulation test, wherein said sequences of entries are referred to as allowable sequences of entries;
• receiving, from the computer-readable storage medium, a second plurality of entries from a failed simulation test of the electronic system, wherein the failed simulation test is a test of the electronic system by simulation that produces results that indicate failures of the electronic system, each of the second plurality of entries includes at least information about simulation time and information from an output electronic waveform description or an output text log file;
• analyzing, with one or more of the computer processors, the second plurality of entries from the failed simulation test based on information related to the first plurality of entries and the allowable sequences from the successful simulation test;
• and
• identifying, with one or more of the computer processors, one or more anomalies in the electronic system based on the analysis of the failed simulation test.

A non-transitory machine-readable storage medium comprising computer code stored in said non-transitory machine-readable storage medium, wherein said computer code, when retrieved from said non-transitory machine-readable storage medium and executed by a processor, results in:

• receiving, from the non-transitory machine-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, wherein the successful simulation test is a test of the electronic system by simulation that indicates the electronic system passing the test, each of the plurality of entries includes at least information about simulation time and information from simulation output;
• determining, with one or more of the computer processors, time sequence relationship between pairs of entries selected from the plurality of entries;
• identifying, with one or more of the computer processors, allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship;
• receiving, from the non-transitory machine-readable storage medium, a second plurality of entries from a failed simulation test of the electronic system, wherein the failed simulation test is a test of the electronic system by simulation that produces results that indicate failures of the electronic system, each of the second plurality of entries includes at least information about simulation time and information from simulation output;
• analyzing, with one or more of the computer processors, the second plurality of entries from the failed simulation test based on information related to the first plurality of entries and the allowable sequences from the successful simulation test;
• and
• identifying, with one or more of the computer processors, one or more anomalies in the electronic system based on the analysis of the failed simulation test.