Tracking array data contents across three-valued read and write operations
AssigneeInternational Business Machines Corporation
InventorsJason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
Life of this patent
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Abstract
A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.
Claims19
A method, in a data processing system, for tracking array data contents across three-value read and write operations in a simulation of an integrated circuit design, the method comprising:
- receiving, in the data processing system, an integrated circuit design having a memory array;
- initializing, by the data processing system, a tree data structure for the memory array having a root node assigning a default value to all data bits, wherein initializing the tree data structure for the memory array comprises creating the root node having a non-deterministic address having a non-deterministic value for all address bits, wherein the non-deterministic address represents a set of addresses, and a data value equal to a default value;
- and
- responsive to a write operation writing a write data value to a write address, updating, by the data processing system, the tree data structure to track memory array contents.
A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
- receive, in the computing device, an integrated circuit design having a memory array;
- initialize, by the computing device, a tree data structure for the memory array having a root node assigning a default value to all data bits, wherein initializing the tree data structure for the memory array comprises creating the root node having a non-deterministic address having a non-deterministic value for all address bits, wherein the non-deterministic address defines a set of addresses, and a data value to a default value;
- and
- responsive to a write operation writing a write data value to a write address, update, by the computing device, the tree data structure to track memory array contents.
An apparatus, comprising:
- a processor;
- and
- a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
- receive an integrated circuit design having a memory array;
- initialize a tree data structure for the memory array having a root node assigning a default value to all data bits, wherein initializing the tree data structure for the memory array comprises creating the root node having a non-deterministic address having a non-deterministic value for all address bits, wherein the non-deterministic address defines a set of addresses, and a data value equal to a default value;
- and
- responsive to a write operation writing a write data value to a write address, update the tree data structure to track memory array contents.
Dependencies are inferred from the claim text.