Receiver for signal communication system with disturbance rejection circuit

A system, comprising:

• a transmitter;
• a galvanically isolated wireless interface having a first antenna coupled to the transmitter and a second antenna;
• and
• a receiver coupled to the second antenna of the galvanically isolated wireless interface and having a disturbance rejection block configured to compensate for parasitic currents flowing between the first and second antennas at potential variations between an input and an output of the galvanically isolated wireless interface, the disturbance rejection block comprising:
• a common-mode disturbance rejection block configured to take up parasitic currents present on the terminals of the second antenna;
• and
• a common-mode voltage biasing block configured to bias received signals.

A receiver, comprising:

• means for amplifying signals received through a galvanically isolated wireless interface;
• and
• means for compensating for parasitic currents flowing between a transmitting antenna and a receiving antenna at potential variations between an input and an output of the galvanically isolated wireless interface, the means for compensating including:
• means for taking up parasitic currents present on terminals of the receiving antenna;
• and
• means for biasing the means for amplifying.

A method, comprising:

• receiving a signal through a galvanically isolated wireless interface having first and second antennas;
• rejecting common-mode transients of the received signal at potential variations between an input and an output of the galvanically isolated wireless interface by:
• taking up parasitic currents present on terminals of the second antenna;
• biasing the received signal;
• and
• amplifying the received biased signal.

A receiver, comprising:

• a disturbance rejection block configured to receive signals from a receiving antenna of a galvanically isolated wireless interface and to compensate for parasitic currents flowing between a transmitting antenna and the receiving antenna at potential variations between an input and an output of the galvanically isolated wireless interface, wherein the disturbance rejection block includes:
• a series of resistors configured to couple between terminals of the receiving antenna;
• a transistor output stage configured to modify a voltage between an intermediate terminal of the resistors and a ground;
• and
• a differential stage configured to receive the voltage between the intermediate terminal of the resistors and the ground and a reference voltage, and to drive the transistor output stage.

A receiver, comprising:

• a disturbance rejection block configured to receive signals from a receiving antenna of a galvanically isolated wireless interface and to compensate for parasitic currents flowing between a transmitting antenna and the receiving antenna at potential variations between an input and an output of the galvanically isolated wireless interface, wherein the disturbance rejection block includes:
• a series of resistors configured to couple between terminals of the receiving antenna;
• two transistor output stages configured to modify voltages at respective ends of the series of resistors;
• and
• a differential stage configured to receive a voltage between an intermediate terminal of said resistors and a ground, and said reference voltage, and to drive the two transistor output stages.