Highly flexible fractional N frequency synthesizer

A communication system, comprising:

• a reference frequency generator which generates a reference clock signal of frequency fref;
• and
• a clock block which includes a PLL for synthesizing a fractional frequency based on the reference clock signal, wherein the PLL further comprises:
• a 1/N frequency divider, wherein N is an integer;
• a voltage-controlled oscillator (VCO) configured to receive a control voltage and generate an output clock signal of frequency fsyn based partly or solely on the control voltage;
• a programmable phase mixer coupled between an output of the VCO and an input of the 1/N frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase difference between the output clock signal and the first clock signal;
• wherein the 1/N frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N;
• a phase detector configured to receive the reference clock signal from the reference clock frequency generator and the second clock signal from the 1/N frequency divider, and produce a phase error by comparing frequency fref with frequency f2, wherein the phase error is used to update the control voltage so that frequency f2 is synchronized to frequency fref;
• and
• a controller coupled to the programmable phase mixer, wherein the controller sends a control signal to the programmable phase mixer to control a phase offset produced by the programmable phase mixer;
• wherein the controller receives a control clock signal of frequency fdig, and wherein the phase offset is computed by evaluating an expression that comprises fsyn, N, fref, and fdig.

An apparatus, comprising:

• a processor;
• a memory;
• and
• a communication module including a PLL, wherein the PLL comprises:
• a 1/N frequency divider, wherein N is an integer;
• a voltage-controlled oscillator (VCO) configured to receive a control voltage and generate an output clock signal of frequency fsyn based partly or solely on the control voltage;
• a programmable phase mixer coupled between an output of the VCO and an input of the 1/N frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase difference between the output clock signal and the first clock signal;
• wherein the 1/N frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N;
• a phase detector configured to receive a reference clock signal of frequency fref and the second clock signal from the 1/N frequency divider, and produce a phase error by comparing frequency fref with frequency f2, wherein the phase error is subsequently used to update the control voltage so that f2 is synchronized to frequency fref;
• and
• a controller coupled to the programmable phase mixer, wherein the controller sends a control signal to the programmable phase mixer to control a phase offset produced by the programmable phase mixer;
• wherein the controller receives a control clock signal of frequency fdig, and wherein the phase offset is computed by evaluating an expression that comprises fsyn, N, fref, and fdig.