Structure for window comparator circuit for clock data recovery from bipolar RZ data
AssigneeInternational Business Machines Corporation
InventorsSantoshkumar Jinagar, Animesh Khare, Ravi Lakshmipathy, Narendra K. Rane, Umesh Shukla, Pradeep K. Vanama
Life of this patent
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Abstract
A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.
Claims21
A hardware clock-data recovery doubler circuit for digitally encoded communications signals, comprising:
- a first level shifter with an output coupled to a first inverter and an input coupled to a second inverter;
- a second level shifter with an input coupled to a third inverter and an output coupled to a fourth inverter;
- a first multiplexer circuit with inputs coupled to outputs of the first and second inverters;
- a second multiplexer circuit with inputs coupled to outputs of the third and fourth inverters;
- a NAND logic gate with a first input coupled to an output of the first multiplexer circuit and a second input coupled to an output of the second multiplexer circuit;
- and
- a fifth inverter with an input coupled to an output of the NAND logic gate and an output coupled to a plurality of transmission gates comprising the first and second multiplexer circuits;
- wherein the output of the NAND logic gate is also coupled to an opposing side of the plurality of transmission gates comprising the first and second multiplexers.
A method for a hardware clock-data recovery doubler circuit for digitally encoded communications signals, comprising:
- providing a first level shifter with an output coupled to a first inverter and an input coupled to a second inverter;
- providing a second level shifter with an input coupled to a third inverter and an output coupled to a fourth inverter;
- providing a first multiplexer circuit with inputs coupled to outputs of the first and second inverters;
- providing a second multiplexer circuit with inputs coupled to outputs of the third and fourth inverters;
- providing a NAND logic gate with a first input coupled to an output of the first multiplexer circuit and a second input coupled to an output of the second multiplexer circuit;
- and
- providing a fifth inverter with an input coupled to an output of the NAND logic gate and an output coupled to a plurality of transmission gates comprising the first and second multiplexer circuits;
- wherein the output of the NAND logic gate is also coupled to an opposing side of the plurality of transmission gates comprising the first and second multiplexers.
A design structure, embodied on a non-transitory storage medium, readable by a machine used in manufacture of an integrated circuit, the design structure comprising:
- a first level shifter with an output coupled to a first inverter and an input coupled to a second inverter;
- a second level shifter with an input coupled to a third inverter and an output coupled to a fourth inverter;
- a first multiplexer circuit with inputs coupled to outputs of the first and second inverters;
- a second multiplexer circuit with inputs coupled to outputs of the third and fourth inverters;
- a NAND logic gate with a first input coupled to an output of the first multiplexer circuit and a second input coupled to an output of the second multiplexer circuit;
- and
- a fifth inverter with an input coupled to an output of the NAND logic gate and an output coupled to a plurality of transmission gates comprising the first and second multiplexer circuits;
- wherein the output of the NAND logic gate is also coupled to an opposing side of the plurality of transmission gates comprising the first and second multiplexers.
A hardware clock-data recovery doubler circuit for digitally encoded communications signals, comprises:
- a window comparator generating a collapsible window;
- and
- a clock output received by the window comparator as feedback;
- wherein based on the clock output the window comparator circuit collapses the collapsible window while sampling input Bipolar return to zero data.
Dependencies are inferred from the claim text.